A 0.62 μW/sensor 82 fps Time-to-Digital Impedance Measurement IC with Unified Excitation/Readout Front-End for Large-Scale Piezo-Resistive Sensor Array
Published in IEEE International Solid-State Circuits Conference (ISSCC), 2026
Status: Published.
This work presents a highly energy-efficient time-to-digital impedance measurement integrated circuit designed specifically for large-scale piezo-resistive sensor arrays. The proposed IC achieves remarkable performance with only 0.62 μW power consumption per sensor while maintaining a high sampling rate of 82 fps. The unified excitation/readout front-end architecture enables scalable sensor interfacing for applications requiring dense sensor arrays with real-time impedance monitoring capabilities.
My Role in This Work
- Basic on the designed IC, I used FPGA to verify the functionality of the whole system including the insole sensor array, the readout IC, and the data processing unit.
- Design the way to calibrate the measured impedance to ensure accurate readings across all sensors in the array.
- Design the readout algorithm to process the raw data from the IC and convert it into meaningful impedance values for further analysis.
- Apply the converted impedance data in downstream applications, such as gait analysis and health monitoring, to demonstrate the practical utility of the sensor array system.
- Design related hardware and software system on a portable platform (NRF52840 + ASIC + IMU + power management).
Recommended citation:
J. Li, Q. Zhang, D. Jiang, S. Ha, A. Demosthenous, and Y. Wu. "A 0.62 μW/sensor 82 fps Time-to-Digital Impedance Measurement IC with Unified Excitation/Readout Front-End for Large-Scale Piezo-Resistive Sensor Array." IEEE Int. Solid-State Circuits Conf. (ISSCC), 2026.
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